Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action and find out how ST Microelectronics is using them to shorten timing debug.

Today’s complex SoCs contain a mix of IP and custom logic with some blocks mature and some still being refined. Sophisticated clocking schemes and not-so-final clock constraints make timing debug difficult. Even worse, global design teams must analyze these designs across multiple modes and corners which makes collaboration and data sharing even more challenging.

This webinar will focus on three topics:

  • How to understand and debug complicated timing paths and clock constraints faster using techniques to highlight clock relationships, visualize physical clock networks, and isolate problems quickly. 
  • A faster way to analyze timing paths from multiple modes and corners simultaneously using PrimeTime’s new light-weight path files that can be 100x smaller than traditional save-session files. 
  • ST Microelectronics experience with worldwide design collaboration and new interactive multi-scenario analysis tool and visualization techniques.

During the webinar you will see demonstrations on how to:

  • Debug complicated clock networks and constraints using visualization techniques to see clock-to-clock relationships and trace physical clock networks. 
  • Quickly find problems with generated clocks and multiple clock convergence or multiple clocks on same pin 
  • Complete timing analysis and debug faster by creating, categorizing, filtering and sharing small, light-weight path files that load quickly, run in small machines and help designers zero in on timing problems. 

This 30 minute webinar will be followed by a Q&A session with our Corporate Applications and R&D teams.

Who should attend 

Designers, managers and system integrators responsible for SoC and ASIC implementation and signoff interested in learning how to track down faulty clocks, constraints and paths quickly to speed debugging.

Speakers:
Robert Landy
Staff Corporate Applications Engineer
Implementation Group
Synopsys

Robert Landy is a Senior Corporate Applications Engineer on the PrimeTime team at Synopsys. He started his career working in IC CAD and then design methodology for mixed signal analysis before moving into EDA in 2002. Robert has been responsible for providing advanced scripting solutions for clock mesh analysis, SI-enabled design flows and gate-level static timing analysis while working as a Corporate Applications Engineer. He received a BS in Electrical and Computer Engineering from University of South Carolina. 

Philip Cuney
Design Support Technical Leader
Design Support & Methodology Group
Home Entertainment & Displays
ST Microelectronics

Philip Cuney is a Technical Leader in the Home Entertainment & Displays division of ST Microelectronics in Grenoble, France. He started with ST Microelectronics as an IC designer, and for the last 15 years he has been in the CAD group. He is currently responsible for the front end portion of the digital design flow where he has focused on the STA environment and timing constraints management.