DDR4 SDRAM is the latest JEDEC standard for commodity DRAM. It supports a higher range of data transfer rates and lower voltages than previous standards and is commonly used in high-performance cloud computing environments, as well as in server, storage, in-memory computing databases, and other applications.

This webinar will describe the best practices that designers should follow for systems-on-chips (SoCs) connecting to DDR4 in their enterprise applications. It will describe system-level methods and chip architectures needed to connect to large amounts of DRAM with high throughput. It will discuss features that will help improve reliability, availability, and serviceability (RAS) for the system’s DRAM, including reducing system downtime by automatically retrying failed memory commands.

Attend this webinar to learn about:

  • Key features of DDR4 for enterprise applications
  • System-level methods to achieve large memory capacity: Registered DIMMs (RDIMMs), Load Reduced DIMMs (LRDIMMs) and 3D Stacked DRAMs (3DS) with Through Silicon Vias (TSVs)
  • Chip architecture and features for connecting to large amounts of DRAM
  • Achieving high-speed connections to large amounts of DRAM
  • Reliability, Availability, and Serviceability (RAS) for DRAM

Who should attend?
System architects and engineers working on enterprise-level applications.


Marc Greenberg, Director of Product Marketing, Synopsys

Marc Greenberg is the director of product marketing for DDR IP at Synopsys. He has 10 years of experience working with DDR Design IP and has held technical and product marketing positions at Denali and Cadence. He has a further 10 years of experience at Motorola in IP creation, IP management, and SoC methodology roles in Europe and the United States. He holds a five-year master’s degree in electronics from the University of Edinburgh in Scotland.