Overview:

One of the most common questions we hear from our semiconductor IP customers at Synopsys is, “How fast will my DDR interface operate in a wire bond package?” The high bond wire inductance of the low-cost wire bond package creates significant challenges to a high-speed, parallel interface such as DDR3 at 1333 to 1600 Mbps. This webinar will compare and contrast two identical test chips using Synopsys DesignWare DDR3/2 PHY and controller IP, the first using a flip chip package and the second using a wire bond package. Culminating in a series of data eye comparisons at up to 1600 Mbps, the participant will see firsthand the real impact of the packaging technology on the DDR interface. The webinar will conclude with an outline of best practices for high-speed DDR interface signal integrity.
Who should attend: Designers of high-performance SoCs or ASICs including one or more high performance DDR SDRAM interface.
Estimated length: 50 minutes, 10 minutes Q&A
Presenter:

Graham Allan, Senior Product Marketing Manager for Memory Interface IP, Solutions Group, Synopsys

Graham Allan, Senior Product Marketing Manager for Memory Interface IP, joined the Solutions Group at Synopsys in June 2007. A veteran of DRAM and memory design, Graham holds 15 patents, has spoken at several industry conferences, and has contributed to the SDRAM, DDR, DDR2 & DDR3 standards at JEDEC since 1992, including holding a chairmanship position from 1996 to 1999.