Overview:
Dealing with change has become more important than ever—whether you need to support a new emerging standard or respond to new functionality that your competition just released. And, as if the drive towards more flexibility and versatility isn’t complex enough, designers also need to deal with growing performance and power efficiency demands while meeting time-to-market pressure.

So what about trading fixed hardware implementation for software flexibility? Is it possible to design blocks that are flexible enough to deal with multiple standards and different use cases and that don’t require major re-implementation and verification when requirement changes occur? Meet custom processors or ASIPs (Application Specific Instruction-set Processors). In this session, you will learn how custom processors can provide the right trade-off between flexibility and power, performance and area requirements. You will also learn how Synopsys Processor Designer greatly eases the internal project dependencies by enabling the creation of the optimized RTL code, software tools and SystemC model for almost any imaginable custom processor from a formal LISA input specification.

Estimated length: 
1 hour including questions

Who should attend:

  • Hardware engineers who are working on complex blocks that need to support multiple standards and/or modes.
  • Hardware engineers who are working on complex control logic.
  • Architects that want to make their design more scalable.
  • Processor designers that want to minimize their support and maintenance load.


What Attendees will learn

  • The motivation for creation and development of custom processors
  • Custom processor requirements and development challenges
  • How Synopsys Processor Designer can meet the requirements and overcome the challenges of custom processor development
  • Real results from implementation of a custom processor replacing fixed hardware

Presenter:
Drew Taussig, Corporate Applications Engineer at Synopsys
Drew Taussig is a Corporate Applications Engineer in the Systems Group at Synopsys, supporting Processor Designer. Drew came to Synopsys from CoWare as part of the Processor Designer Product Team. Prior to CoWare, Drew led the ASIC Systems Architecture Team at Philips Semiconductors (now NXP). Drew has a Masters Degree in Electrical Engineering from Stanford University and a BS in Electrical Engineering and Computer Science from the University of Colorado at Boulder.