Overview:
As an alternative to ASICs and ASSPs, FPGAs enable manufacturers of digital electronic systems to accelerate new products to market and increase product differentiation while reducing cost and risk. The latest generation of FPGAs offer increases in performance, capacity, and built-in capabilities that make them suitable for implementing a greater portion of critical system-level functionality. However, the trends of higher performance, increased integration, and smaller form factors create challenges in managing power consumption and thermal dissipation. As a result, engineers are increasing their focus on power consumption as a consideration for component selection and techniques for power management are becoming more important to successful system design.

Xilinx has adopted a holistic approach to ensure system designers can achieve power-optimized designs with Virtex®-6 and Spartan®-6 FPGAs. In this webcast we examine the factors that contribute to FPGA power consumption and review the measures Xilinx has taken regarding process and device architecture to control power. We also present tools, design techniques, and new device options that enable engineers to create FPGA-based designs that achieve demanding performance goals with strict power budgets.

Webcast Attendees Will Learn:

  • The factors that can influence power in an FPGA design
  • How to utilize the Spartan-6 and Virtex-6 FPGA features, tools, and device options to reduce overall power consumption
  • How Xilinx has simplified power optimization by taking a holistic approach to designing lower power FPGAs
  • Features and techniques to simplify power system designs

    • Who Should Attend:

  • Hardware system designers
  • System architects
  • Project managers
  • PCB designers

    • Presented By:
    Matt Klein
    Principal Engineer – Product and Market Development Group

    Matt's principle concentration has been in the area of power consumption, especially with Virtex-4, Virtex-5, and all of Xilinx's future products. Matt has worked at Xilinx for 4 years and has worked with FPGAs for > 20 years having done close to 50 FPGA designs and worked on the system architecture of several large products. During this time Matt was the System Architect and Hardware Technical Lead at both Hewlett Packard (15 years) and Pinnacle Systems (5 years) with products ranging from Digital Synthesizers to Digital Radio Bit Error Rate Testers and most recently to Video Servers. Matt has patents in both Digital Radio and Video Systems and Xilinx FPGA patents. Matt has a B.S.E.E from Case Western Reserve University and an M.S.E.E. from Santa Clara University.