Overview:
With the development of next generation communications, networking, and consumer electronics products, the desire for higher memory performance and density continues to grow. At the same time, consumers and manufacturers are demanding solutions that offer lower initial costs as well as lower operating costs, preferably with less environmental impact. This means that while the memory performance and density requirements are going up, the memory cost and power requirements are headed in the opposite direction, making the system designer's job increasingly difficult.

Fortunately, Xilinx designed the Virtex-6 and Spartan-6 FPGA families to support faster, less expensive, and lower power memory interface solutions. The Virtex-6 controller for DDR memory standards (DDR2, DDR3) includes transaction reordering capabilities that enable significantly higher levels of efficiency than previous generations or competitive controllers. And with data rates up to 1066 Mbps or more, the Virtex-6 controller offers a substantial jump in total memory bandwidth.

Spartan-6 devices include two to four dedicated embedded multi-port memory controller blocks (MCBs) that enable simple connection to four common memory standards: DDR3, DDR2, DDR, and LPDDR (Mobile DDR). And with data rates up to 800 Mbps for the dedicated MCB blocks, Spartan-6 devices double the memory interface performance relative to past generation and competitive low cost FPGA solutions. There's also the power saving benefits associated with having a dedicated memory controller, particularly one that supports the low power DDR (LPDDR) standard.

In this webinar, Xilinx will introduce the memory interface solutions for Virtex-6 and Spartan-6 devices and explain how to use these solutions to get the most out of your external memory in your next FPGA design.


Web seminar attendees will learn:

  • DRAM industry trends and roadmaps
  • How the Virtex-6 Memory Controller reaches new levels of performance and efficiency
  • How the Spartan-6 Memory Controller improves performance while lowering cost and power
  • Who should attend:

  • FPGA designers
  • System Architects
  • Presenters:
    Derek Curd, Technical Marketing Manager for Memory Interface Solutions
    Derek Curd has over 15 years of experience in the definition, design, manufacturing, and marketing of programmable logic devices and holds more than 25 patents in the programmable logic and semiconductor field. In his role as a Xilinx Technical Marketing Manager, Derek is responsible for future product definition, IP roadmaps, and general solution strategy for external memory interfaces. Derek holds B.S. and M.S. degrees in Electrical Engineering from the Massachusetts Institute of Technology.

    Adrian Cosoroaba, Marketing Manager, Technical Marketing
    Adrian Cosoroaba is responsible for marketing activities related to Memory Controller and Interface Solutions. He brings to Xilinx over 20 years of semiconductor experience in memory applications and marketing. Prior to joining Xilinx, he held a range of applications engineering and strategic marketing positions at Fujitsu and helped define through JEDEC the DDR SDRAM and SSTL I/O standards. He holds an M.S. in Electrical Engineering from Ohio State University and a B.S. in Engineering Physics from University of California at Berkeley.