Successful low-power IC designs implement several power management schemes through a comprehensive design, implementation and verification tool chain that understands the power intent. These designs include a large portion of embedded memories that may dominate the chip’s power allocation. Challenged by the increasing embedded memory count driven by the rich A/V content in today’s consumer products, SoC designers must focus on minimizing power while maximizing performance and density.

What you will learn:

  • How to minimize low-power design complexity with IP that is optimized for power, performance and density
  • The trade-offs and practical implementation of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning
  • How the DesignWare® IP portfolio of SiWare™ Embedded Memories and STAR Memory System® embedded test & repair solution are suitable for a wide range of high-performance SoC applications such as graphics, networking, storage and mobile handsets.

Who should attend: Designers that are or will be designing complex SoCs with rich A/V content in 40nm or 28nm technology nodes.

Estimated length:
 50 minutes, 10 minutes Q&A

Prasad Saggurti
Product Marketing Manager, Synopsys
Prasad Saggurti is the Product Marketing Manager for Embedded Memory IP at Synopsys. Prior to Synopsys, Prasad held senior engineering and marketing roles at MoSys, ARM, National Semiconductor and Sun Microsystems. Prasad has an MSEE from the University of Wisconsin-Madison and an MBA from the University of California-Berkeley.