Conquering On-chip Memory Bandwidth Bottlenecks
Memory bandwidth challenges are increasing with next-generation high-bandwidth technologies and designers are looking for new cost-effective approaches for resolving bandwidth and efficiency issues on-chip. Today’s popular home entertainment and mobile devices require an increasing number of processors that are dependent on sharing the same pipe, which has generated a sizeable efficiency bottleneck for SoC designers and system architects. Designers often need to add more pins, ports and ultimately more DRAM to boost performance and achieve their design objectives—which translates to unexpected incremental costs. The challenge is for designers to get additional raw bandwidth, derive increased efficiencies on-chip and streamline DRAM management while still getting to market on time and on budget.
In this webinar, Sonics will specifically discuss and highlight:
- Innovative, cost-effective approaches to alleviate memory efficiency congestion in high-bandwidth applications (such as video streaming in devices like PMPs, smart phones, HDTVs, Set-top-boxes, DVRs and digital cameras)
- Increasing memory bandwidth utilization up to 85% without additional memory costs, system degradation or re-design
- Resolving the ongoing challenge of DRAM efficiency on-chip
- Getting to market quicker and ahead of schedule by automatically tuning your SoC
Who should Attend:
- SoC designers, developers and system architects working on high-bandwidth applications such as video
- Designers developing the next generation of low-cost SoCs for the HDTV market
- Designers developing applications processors to support 4G networks
Alex Chao, Director of Corporate Application Engineering, Sonics, Inc.
Alex Chao is the Director of Corporate Application Engineering for Sonics, Inc. Alex and his team are responsible for both pre- and post-sales technical support in North America, and additionally managing technical support for major accounts worldwide. Alex’s background includes baseband processor designs that are extremely power-sensitive as well as high-performance digital video application SoCs. From high level system partitioning, performance modeling, design validation, flow automation and timing closure, Alex has helped customers achieve their design goals using Sonics’ solutions. Prior to Sonics, he worked on network processor designs, Infiniband Data Cluster systems and various UNIX workstations. Alex received a B.S. in EE from Chinese Culture University, and his master’s degree in EE from Polytechnic University (now part of NYU).
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