Cadence Functional Verification Webinar Series
Are you concerned about improving verification productivity? Wondering about how to automatically leverage the power and performance of formal analysis tools for mundane tasks? Are you building a mixed-signal SoC and pondering how best to verify that mixed-signal block? Curious about how to maximize your investment in the Universal Verification Methodology (UVM)?
Join Cadence® verification experts for a series of technical webinars on the most relevant topics in functional verification. We’ll introduce you to the latest techniques, best practices, methodologies, and support services you need for designing and verifying your silicon designs.
In these concise, 1-hour sessions, our technical experts will address hot topics including the UVM, assertion-based simulation, metric-driven verification, automated scoreboarding, register map verification, and more.
- Discover possible solutions and best practices to tackle your toughest verification problems
- Learn new applications and methodologies to boost productivity and profitability
- Ask questions and get the answers you need to adopt new approaches
- Follow up with our technical field experts and hone your skills using the Incisive Verification Kit
These webinars are designed to be methodology-and application-based, not a marketing pitch. Plus, you don’t need to travel-you can view these presentations and demonstrations from the comfort of your home or office!
Cadence Functional Verification Webinar Topics — Helping You Achieve Silicon Realization
- Aug 23, 9am PDT – Finding the Bugs in Your UVM Haystack
- Sep 8, 9am PDT – Ending the Debate – Apples or PCs? & e or SystemVerilog?
- Sep 15, 9am PDT – Applying Digital Verification Methodologies to Analog Design
- Oct 13, 9am PDT – Automate Assertion Generation for Simulation, Formal, and Emulation Flows
- Oct 20, 9am PDT – Oceans of Expertise Connecting the UVM to Sea (C /C++/SC)
- Nov 3rd, 9am PDT – What Metrics Matter – A User’s Perspective on Coverage
- Nov 17, 9am PST – Quickly Find Data Transport Bugs with Formal Scoreboarding
- Dec 1, 9am PST – Set Your UVM Runtime Phases to Maximum Power
- Dec 15, 9am PST – Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff
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