Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High Speed Memory Interfaces
Each memory transaction requires that signaling must meet set up and hold requirements for a given frequency. In fact, there are several timing domains that must be satisfied for each transaction.
- DQ, data, timing must meet set up and hold timing to the rising and falling edges of the DQS, strobe, signal. For Writes and Reads, this is the double data rate timing domain.
- The Address, Command and Control signals are single data rate signals whose set up and hold times are measured to the rising edge of the differential CK/CK#. These signals are typically more heavily loaded then the DQ signals. Address and Command signals can be, and often are, routed to every device on the interface. Loading of the Control signals is limited to a single rank.
- DQS to CK/CK# timing. The rising edge of each DQS signal must arrive at the memory within +/- ¼ of a clock period of the Rising edge of the differential CK/CK#. This is relatively simple to maintain for DDR2 with a minimum skew of 469 ps at 1067 Mbps. DDR3 implements an address routing technique referred to as fly-by, where devices are daisy-chained along the Address net. This can lead to large skews between CK/CK# and DQS, requiring the implementation of Read and Write leveling.
Each of these interfaces are source-synchronous, requiring the strict maintenance of skew and other uncertainty effects. For each of these interfaces, the contributors can be assigned to:
- The transmitter
- The interconnect
- The receiver
This webinar will discuss the impact of these sets of contributors, with emphasis on signal integrity techniques to address margin eroders such as crosstalk, simultaneously switching outputs, impedance mismatch and inter-symbol interference.
Estimated Length: 1 hour
Who should attend: SoC design engineers, managers and architects; package engineers; and PCB designers.
Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).
In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).
John Ellis is a Senior Staff Research & Development Engineer specializing in system-level signal integrity analysis. He was a co-founder of TriCN, Inc., a circuit IP company based in San Francisco, California. He has authored several patents in the field of high speed interconnect.
Please disable any pop-up blockers for proper viewing of this webinar.