Building robust 6.5Gbps serial links with Virtex-5 FPGAs: Design considerations for first-pass success
To satisfy ever increasing bandwidth requirements, system designers are pushing serial I/O interfaces to higher speeds with next generation protocols such as PCI Express® and Interlaken. In this webcast we review the challenges that engineers face when designing multi-gigabit interfaces and present solutions for ensuring the signal integrity required for successful system design.
Webcast Attendees Will Learn:
- Common serial link hardware issues
- The advanced equalization capabilities built into the GTX transceivers available on Virtex®-5 FPGAs
- The solutions Xilinx is providing to help you build reliable high-speed links
Who Should Attend
Panch Chandrasekaran is marketing manager for Xilinx(www.xilinx.com) high-speed connectivity solutions. Panch’s background is in analog and mixed-signal design of 2.5 Gbps and 10 Gbps transceiver chips for telecom applications. He has also held high-speed application engineering positions dealing with multi-gigabit signaling and signal integrity. Panch has a MSEE from University of Central Florida.
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