Building Optically Compliant High Performance Serial Links at 10G, 100G and 400G
In order to meet increasing bandwidth demands, communication equipment vendors are building 40G, 100G and looking toward to the next generation 400G systems with as few changes to the existing infrastructure as possible. They demand more of the Programmable Platforms and semiconductor chips that interface with the optical modules both in terms of functionality as well as performance to double bandwidth capacity, to maintain power density and to lower costs. This webcast elaborates on the design requirements—architecture, circuit techniques, and system level considerations—to build optically compliant serial interfaces for the 40G/100G and 400G systems.
In this webcast, attendees will learn:
- Review of design requirements—architecture, circuit techniques and system level considerations to build optically compliant serial interfaces
- Key challenges and interfaces for designing 100G to 400G systems and user benefits when using Xilinx transceiver technology
Panch Chandrasekaran, Senior Marketing Manager, Serial IO
Panch Chandrasekaran is Senior Marketing Manager for Serial IO at Xilinx, responsible for product management of Serdes-based FPGAs across Wired, Wireless, Video and Defense market segments. Panch’s responsibilities span product strategy and definition, product launch as well as customer and field enablement. Prior to Xilinx Panch worked as a high speed signal expert designing 2.5 Gb/s through 40 Gb/s circuits. Panch has a MSEE in Device Physics from University of Central Florida and an MBA from UC Berkeley Haas School of Business.
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