The continuing trend for larger, more complex designs has made it more critical than ever for verification engineers to increase their productivity. One generally accepted solution to the productivity demand is to employ constrained random verification as the mainstay verification methodology and utilize reusable verification IP. While constrained random verification takes better advantage of compute resources by providing more testing with less test code development time, setting it up can pose its own set of challenges as well.

In this webinar:

  • Discover how to take advantage of the constrained random verification approach and work through the challenges
  • Learn how to successfully implement the key features that are necessary to build a constrained random verification environment
  • See the step by step methods and techniques for using DesignWare Verification IP in conjunction with Synopsys' proven VMM Methodology Standard Library for SystemVerilog to develop a robust verification environment, some of which include:
    • Configuring, connecting and instantiating the Verification IP
    • Simple directed and random tests
    • Functional coverage
    • Message control
    • Connecting scoreboards

Estimated length: 1 hour

Who should attend: SoC verification engineers, managers and architects


Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).

In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).


Steven McMaster, Senior Staff Engineer, works with Verification IP (VIP) at Synopsys and has been involved in EDA tools for 20+ years. The majority of his years have been spent in the verification arena with a few years spent developing schematic capture and board design tool. Currently Steven is an engineering lead for the Synopsys OCP VIP and the chair of the OCP-IP Functional Verification Working Group. He was a core team member for both the AXI and OCP VIP development efforts, and has also been involved in the ongoing development for most of the existing Synopsys VIP products. His main focus on these projects/products has been in the areas of functional coverage, assertions, SytemVerilog, and VMM. Steve is also a blogger on the "Inside Protocol Verification" blog, check it out here: http://synopsysoc.org/insideprotocolverification/.