Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Please join us for an in-depth technical webinar focused on new capabilities in DFTMAX™ compression and TetraMAX® ATPG that efficiently manage tester power and screen hard-to-detect defects.
Conventional test compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop, overheating, and test program failures. Separately, manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures, and expensive silicon returns. These two combined trends effectively increase the cost of test.
During this webinar, we will provide an overview of new capabilities in DFTMAX compression and TetraMAX ATPG that manage device power consumption at the tester, resulting in higher yield. Also, we will review technology developed at Synopsys that can help you create tests to detect defects creating small delays, thereby increasing your manufacturing test quality.
Who Should Attend?
DFT Engineers, Design Engineers and Engineering Managers
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