This webcast is an overview of the best techniques for the optimal layout of Frequency Synthesizers, with a particular emphasis on Phase Locked Loops (PLLs).

  • Achieve the best performance from PLL devices.
  • Minimize spurious emissions from PLLs.
  • Ensure minimal interference from Frequency Synthesizers to neighboring circuits.

Who Should Attend: Design engineers in the following disciplines: RF & Microwave Systems, High Speed Mixed Signal, Instrumentation, and Communications.


Ian Collins, Applications Engineer, Analog Devices

Danny Basler graduated from the University of Paisley in the UK with a bachelor degree in Electronic & Electrical Engineering. He joined NXP in 2002 and has held several positions in Automotive and Industrial Microcontroller product marketing as well as account management.