Avoiding the Landmines When Using a DDR Interface on your Next SoC
More and more SoCs are turning to the "almost free" DDR2 or DDR3 SDRAM to satisfy their off-chip memory storage requirements for their SoC designs. OK, DRAMs may cost a buck or two each but most SoC designers are unfamiliar with the realities of the DRAM market. Unless you are a regular attendee at the JEDEC industry standards meetings for DRAM, it is very difficult to decipher how the memory market is going to unfold. And even if you do attend the JEDEC meetings, there is no standard for the memory controller or memory channel, only the DRAMs. Finally, don't even attempt to decipher DRAM pricing!
This webinar will outline and discuss common misconceptions of the DRAM market including:
- The realistic commodity DRAM roadmap for DDR2, DDR3 & LPDDR products
- Including how the speed grades get rolled out
- How the PC market drives the DRAM market and your SoC needs follow in the wake
- When you should consider DDR2, DDR3 or LPDDR
- Speed matters!
- Power matters!
- Size matters!
- Width matters!
- Price matters!
- DDR3 "gotchas"
- Memory controllers cannot be built to DRAM standards
- How the controller is different from the DRAM
- Driving DIMMs vs. components
- Why you should care!
- How the DRAM interface can affect your SoC design & package criteria
- Pin count
- Package type
- Package power planes
Estimated Length: 45 minutes
Who should attend: SoC design engineers, managers and architects.
Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).
In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).
Graham Allan, Senior Product Marketing Manager for Memory Interface IP, joined the Solutions Group at Synopsys in June 2007. A veteran of DRAM and memory design, Graham holds 15 patents, has spoken at several industry conferences, and has contributed to the SDRAM, DDR, DDR2 & DDR3 standards at JEDEC since 1992, including holding a chairmanship position from 1996 to 1999.
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