Specialized processors have long been used as a secret weapon by designers to develop highly differentiated products optimized for specific performance, power and cost requirements of an application. Deploying an in-house processor requires the creation and maintenance of a software development kit (SDK), and at a minimum the SDK has to provide an assembler, linker/loader, instruction-set simulator and debug mechanism. Beyond that, SDK users need fully-featured graphical/interactive debuggers and most importantly, compilers to handle the complexity of today’s software projects.

Developing an SDK is extremely time consuming and requires special skills. Open source projects such as LLVM, GDB, and Eclipse have given designers a head-start in building a custom SDK, but it still requires time, effort and expertise. Furthermore, once an SDK has been developed for an in-house processor, you have to consider the ongoing maintenance and support for that SDK.

In this webinar, viewers will learn:

  • The requirements for an SDK, including exploring different architecture techniques such as specialized instructions, parallel-instruction dispatch (including VLIW), vector (or SIMD) support, and specialized data types.
  • How using Synopsys’ ASIP Designer tool can significantly shorten the time and effort of creating an SDK.
  • How ASIP Designer helps you deliver a fully-featured SDK (with an optimizing compiler, graphical/interactive debugger and simulator), and minimize the maintenance and support effort required over the life of the processor.

Who should attend:

  • Processor designers who need to develop an in-house SDK
  • Project managers considering in-house processors and the development and maintenance costs associated with it
  • HW engineers who need more flexibility in their designs
  • Embedded SW engineers who want to understand what they can expect from a compiler for very specialized architectures


Steve Cox manages business development for processor technologies for Synopsys in North America. He started his career as a processor designer at Motorola in Austin, Texas, and was among the many engineers who turned the promise of RISC architectures into reality. Later in his career, Steve developed novel techniques for transaction-based verification of SoCs, which provide the foundation for advanced verification methodologies such as UVM. Through his career, Steve worked on design and verification of processor-based systems at companies ranging from Solbourne, Apple, Nortel, Intel, and Cisco. Today, Steve brings his deep expertise in processor design, hardware design, and high-level design methods to bear on the problems faced by today’s SoC design teams.