An introduction to the efficient 12-pin HyperBus™ Interface and HyperFlash™ Memory
Embedded design engineers need high-speed solutions to address the instant-on and interactive graphical user interface (GUI) requirements of next-generation electronics. The newly announced Spansion,® HyperBus,™ Interface will enable a wide range of high-performance applications, such as automotive instrument clusters, infotainment / navigation systems, advanced driver assistance systems (ADAS), hand-held displays, digital cameras, projectors, factory automation, medical diagnostic equipment, and home automation appliances.
Learn how this efficient 12-pin interface dramatically improves read performance within a system between controllers, memory and other peripherals in the future. The Spansion HyperBus Interface is being implemented broadly by leading system-on-chip (SoC) manufacturers, such as Freescale, which will be launching a number of Freescale Microcontrollers in the near future taking advantage of this new interface.
Spansion will also discuss the first product leveraging the advanced HyperBus Interface, Spansion HyperFlash Memory. This first family of products feature read throughput of up to 333 megabytes per second,—more than five times ordinary Quad SPI flash currently available with one-third the number of pins of parallel NOR flash.
Attendees Will Learn:
- The value proposition of Spansion’s new HyperBus Interface and HyperFlash Memory
- How HyperBus Interface signaling and protocol works.
- How higher memory throughput will enable new memory subsystem architectures potentially removing DRAM.
- Applications that can take advantage of HyperFlash Memory
Who Should Attend:
- Embedded designers that need more performance in their system
- Systems Engineers performing cost / power / performance trade-offs
Senior Director of Product Line Management, Flash Memory Group, Spansion
Hiro Ino, Senior Director of Product Line Management for Spansion’s Flash Memory Group, has been with the company for approximately 9 months. Mr. Ino’s experience in the hi-tech industry started as a system design engineer being part of a development team for designing 3D-graphics supercomputers at Evans & Sutherland. Through his career, his contribution has evolved from engineering and engineering management to business management. Among his latest experiences include: Senior Director of Strategic Business Development at SanDisk, VP of Marketing and Business Development at m-systems (which was acquired by SanDisk), VP of Marketing at T-RAM Semiconductor, a high-profile venture-backed start-up developing a novel high-performance RAM technology, and Director of WW Memory Business at Sony Electronics developing ultra-high-speed memory for CPU cache applications. Mr. Ino received his degrees in Electrical Engineering and Computer Sciences from the University of California at Berkeley.
Cliff Zitlaw, Fellow, Spansion
Cliff Zitlaw has 28 years of experience in the non-volatile memory industry. He has authored several articles and is the inventor or co-inventor of more than 20 patents related to memory architectures. He has previously served as the JEDEC Chair of JC42.2 covering low power PSRAM devices and is currently Spansion’s representative on JEDEC’s Board of Directors. Cliff has been with Spansion for four years and is currently a Spansion Fellow. Prior to joining Spansion he held technical positions at Xicor, Tunitas Microsystems and Micron.
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