Advanced Yield Analysis and Optimization with 3 to 6 Sigma Statistical Simulations for Memory, Logic, Digital and Analog Designs
Handling process variations in process
development, SPICE modeling and design optimization has become a big challenge,
yet a must for advanced process nodes. This Webinar will demonstrate how to make
statistical yield analysis (3-6 sigma) more practical, more reliable and faster,
by fully utilizing the foundry SPICE models, integrated statistical SPICE engine
and hardware-validated statistical sampling technologies. Attendees are invited
to discuss with ProPlus and IBM experts, and learn about the technologies,
solutions and application experience sharing in these related areas.
Who should attend:
Engineers and management who may:
- Have problems and concerns in foundry SPICE models, especially the
statistical variation models
- Be concerned about process variations in advanced process nodes and want to
make better use of foundry variation models
- Be looking for better solutions on statistical yield analysis with regular
Monte Carlo simulations for analog designs
- Need an integrated solution for High Sigma Monte Carlo analysis for your
memory or digital designs
- Be interested in learning about High Sigma design and application
experiences shared by an IBM expert
What attendees will learn:
- How process variations are handled by advanced SPICE models and understand
how to better use those models and make them application specific.
- The keys to a practical yield analysis solution and how to make it more
reliable and faster.
- The technologies and the seamlessly integrated DFY solution from ProPlus,
covering the advanced modeling solutions, high performance high accuracy
statistical SPICE simulation engine and hardware-validated statistical sampling
- The experience sharing on yield analysis and design optimizations from IBM
experts, especially High Sigma analysis for memory designs.
Bruce McGaughy, Chief Technology Officer and Senior Vice President of
Engineering, ProPlus Design Solutions, Inc.
Dr. Bruce McGaughy
currently serves as the Chief Technology Officer and Senior Vice President of
Engineering of ProPlus Design Solutions, Inc. He was most recently the Chief
Architect of Simulation Division and Distinguished Engineer at Cadence Design
Systems Inc., responsible for all Cadence simulation products and technologies,
including Spectre/SpectreRF, APS, UltraSim, etc.
Rajiv V. Joshi, Research Staff Member, T. J. Watson Research Center,
Dr. Rajiv V. Joshi is a research staff member at T. J. Watson
research center, IBM. He received his B.Tech degree from Indian Institute of
Technology (Bombay, India), M.S. degree from Massachusetts Institute of
Technology and Doctorate in Eng. Science from Columbia University, USA. He
developed novel interconnect processes and structures for Aluminum, Tungsten and
Copper technologies, which are widely used at IBM for various sub-0.5um memory
and logic technologies as well as across the globe. His circuit related work
includes design of register files, registers, latches, L1, L2 Caches,
development of physical design tools, and CAD-based library generation and
circuit designs in SOI technology. He received an outstanding technical
achievement award for his contributions to IBM microprocessor designs. His
recent work related to 8T stable 6 GHz SRAM cell was covered by EE times.
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