In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. In this webcast will discuss how the new advanced use modes and capabilities of the HAPS® High-performance ASIC Prototyping System™ with the new HAPS Universal Multi-Resource Bus Interface (UMRBus) can provide users with the components necessary to improve the overall design, verification and software development of an ASIC or SoC. We will demonstrate how users will benefit from a streamlined or faster way to configure their prototyping system for system bring-up and running tests and share information on how existing HDL testbenches from software simulation can be re-used to verify that the RTL design was properly implemented across a multi FPGA-based prototype. And finally, we will discuss how to accelerate system verification with transaction-level modeling and links to virtual prototyping. 

What attendees will learn:

  • Flexible application-level programming interface for most efficient design interaction and debugging
  • Higher productivity through remote prototype management
  • Faster system bring-up through co-simulation capability
  • Accelerate system verification with transaction-level modeling and links to virtual prototyping

Michael Posner, Product Manager, FPGA-Based Prototyping Solutions, Synopsys
Michael (Mick) Posner joined Synopsys in 1994 and is currently a Product Manager for Synopsys’ FPGA-Based Prototyping Solutions. Previously, he has held various application consultant and technical marketing manager positions at Synopsys. He holds a Bachelors Degree in Electronic and Computer Engineering from the University of Brighton, England.