You are invited to attend a series of technical webinars where you will learn a more predictable path to higher quality silicon. Whether you are designing low-power, mixed-signal designs, or you need to boost verification efficiency and throughput, these webinars will show you new approaches to improving your productivity, predictability, and profitability. Hear from myriad technical experts on the topic of silicon design, implementation, and verification. Learn how to maximize your investment in the UVM. Find out how to achieve a predictable and convergent path to closure. Learn how to eliminate bugs with formal verification, and enhance design team collaboration.

Who should attend

Attend these webinars if you are an engineer in the areas of design, implementation, and verification, if you care about increasing productivity, and if you’re looking for new approaches to realizing silicon.

What you will learn

  • Manage parasitics effectively in the front end and back end
  • Improve both verification productivity and design team collaboration
  • Eliminate connectivity bugs with formal verification
  • Perform top-level mixed-signal SoC verification
  • Achieve the next level of verification productivity