Addressing Challenges at 20nm: A Foundry and EDA Perspective
and Samsung jointly present some key challenges of designing and
manufacturing at 20nm. As foundry and design leader in the market,
Samsung will present the foundry perspective of challenges seen at 20nm
and Synopsys will focus on the 20nm challenges faced by designers and a
solution that handles the effects of Double Patterning Technology (DPT)
during physical design and verification.
Dr. Kuang-Kuo Lin, Ph.D.
Director, Foundry Design Enablement
Samsung America Headquarters (Device Solutions)
Kuang-Kuo “KK” Lin is a director of Foundry Design Enablement at
Samsung America Headquarters (Device Solutions). Prior to joining
Samsung, KK had held engineering and management positions at
GlobalFoundries, Chartered, Intel, Cadence and HP. Dr. Lin has
considerable experience in design and process development including DFM,
tapeout flows, layout migration/compaction, custom layouts, full-chip
integration/planning/place and route, and technology CAD (TCAD). He
received his B.S., M.S. and Ph.D. degrees in electrical engineering and
computer sciences from the University of California at Berkeley.
Dr. Tong Gao
Dr. Tong Gao is a Synopsys Fellow. Tong has been with Synopsys for
more than seven years leading routing technologies and is the architect
of IC Compiler Zroute. Before Synopsys, Tong was responsible for routing
technologies in Monterey Design Systems, Avant!, and Silicon Graphics.
He received his BS, MS, and Ph.D. degrees in Computer Science from
University of Illinois at Urbana-Champaign.
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