Achieving 1-TFLOPS Performance with 28-nm FPGAs
Is 1 TFLOPS possible on a single FPGA? At 28 nm, Altera’s Stratix® V FPGA, with its unique variable-precision digital signal processing (DSP) architecture, is equipped to deliver this performance level. This architecture combines the implementation efficiency of common DSP functions such as fast Fourier transforms (FFTs) and finite impulse response (FIR) with the best support for higher precision and floating-point signal processing.
Watch this 30-minute webcast to learn how:
- Our new fused datapath design flow is the only tool that can synthesize floating-point datapaths within an FPGA
- Our Stratix V FPGAs provides the hardware resources required for TFLOPS performance
- Our extensive library of floating-point intellectual property (IP) cores streamline the DSP design process
Mike Parker, Senior Technical Marketing Manager, IP and Technology Product Marketing
As senior DSP technical marketing manager, Michael Parker is responsible for Altera’s DSP-related IP, and is also involved in optimizing FPGA architecture planning for DSP applications. Mr. Parker joined Altera in January 2007, and has over 20 years of DSP wireless engineering design experience with Alvarion, Soma Networks, TCSI, Stanford Telecom and several startup companies.
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