Achieve Lower Silicon Cost Using Embedded Memory Test and Repair
Embedded memories are the most dense components
within a system-on-chip (SoC), accounting for more than 50 percent of the chip
area. Designed using aggressive design rules, embedded memories tend to be more
prone to manufacturing defects and field reliability problems than any other
core on the chip. In order to achieve lower silicon cost it is critical that
embedded memory test and repair solutions provide superior test quality and
yield optimization. Additionally, these solutions need to improve design
productivity by providing a performance-, power- and area-optimized hierarchical
architecture for today’s complex designs, along with seamless integration with
design implementation flows, to achieve quick design closure and faster time to
volume production. In this webinar, we will discuss advanced embedded memory
test solution capabilities including hierarchical implementation and validation,
fault detection in very deep submicron technologies, repair at the manufacturing
level, diagnosis for process improvement and field repair and error correction
(ECC) capabilities that address today’s design yield and reliability needs.
What you will learn:
- The technical trends and challenges associated with embedded test, repair
and diagnostics in today’s designs.
- The trade-offs and design impact of various solutions.
- How Synopsys’ DesignWare® STAR Memory System® can meet your embedded test,
repair and diagnostics needs.
Estimated length: 50
minutes, 10 minutes Q&A
Dr. Yervant Zorian, Chief Architect for embedded test & repair products,
Dr. Zorian is the Chief Architect at Synopsys for embedded
test & repair products in Mountain View, California.
was Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice
President and Chief Scientist of Virage Logic and Chief Technologist at
LogicVision. He received an MS degree in Computer Engineering from University of
Southern California, a PhD in Electrical Engineering from McGill University, and
an MBA from Wharton School of Business, University of Pennsylvania.
is currently the President of IEEE Test Technology Technical Council (TTTC),
General Chair of Design Automation Conference (DAC), the Editor-in-Chief
Emeritus of Design & Test of Computers, the founder & chair of IEEE 1500
Standardization Working Group, and an Adjunct Professor at University of British
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