DDR4 has enabled memory designs to achieve new
performance levels in enterprise, mobile, and personal computing applications.
Accurately capturing and analyzing DDR4 memory traces is critical in bringing
new products to market quickly. See the latest techniques for easily accessing
signals and performing debug, turn-on, interoperability, validation and
compliance testing of DDR4 based designs.

In this webcast learn how to:

  • Gain insight into design violations using logic analysis
  • View complete system functionality
  • Easily trigger on DDR4 memory violations
  • Perform DDR4 compliance testing

Who should attend: High
speed DDR memory design, test, and validation engineers

Grosslight, Memory Product Manager, Digital Debug Solutions, Electronic
Measurement Group, Agilent Technologies, Inc

Jennie Grosslight is
the Product Manager of Agilent’s Digital Debug Memory Solutions where she is
responsible for Agilent’s logic analysis and compliance test tools for Memory

Jennie has worked more than 20 years at Hewlett Packard
and Agilent Technologies in a variety of roles for both Oscilloscopes and Logic
Analyzers, including R&D engineer, Technical Marketing Engineer, and Product
Marketing Engineer. Jennie has been focused on helping customers analyze and
validate memory systems for the past 8 years. She has a degree in Electrical
Engineering from the University of Colorado at Colorado Springs.

Moser, Software Design Engineer, FuturePlus Systems

Greg Moser is a
software design engineer for FuturePlus Systems. In addition to writing protocol
decoders for products Greg is also responsible for technical support and
training. He has been the direct technical support for the past 10 years.

Greg has worked for FuturePlus Systems for over 13 years; he has been
involved with writing software as well as product validation and testing. Prior
to FuturePlus Systems, Greg worked as a senior electronic technician
troubleshooting various main frames for Digital as well as high performance
computers/servers from Sun Microsystems. Greg holds a BS in Information Systems
with a minor in Engineering from the University of Massachusetts.