Accelerate your FPGA Design Schedules with Synplify Premier
FPGA device density is continuing to grow at approximately 2x per node, which is driving more complex and larger FPGA designs. As the complexity grows, FPGA designers are under increasing pressure to accelerate designs and achieve a faster time to market. This is requiring FPGA designers to segment the design process into multiple phases to gain productivity improvements at each phase. These phases include design assembly, initial design bring-up, performance tuning and system debug. At every phase, FPGA designers need sophisticated synthesis tools to help automate and accelerate the individual tasks. This webinar will detail how Synplify Premier supports each design phase through improvements in automation, constraint setup, technologies to achieve the best timing QoR and debugger integration for fast in-system debug.
Attend this webinar to learn about:
- Set up the design for automated synthesis using IP from disparate sources
- Quickly bring up an initial functioning design utilizing methodologies for correct constraints setup and new distributed synthesis with multiprocessing technology to improve runtimes by up to 3X
- Tune a design to achieve timing closure using advanced synthesis and finding optimum P&R settings automatically
- Debug a design on the board by efficiently identifying exact debug states and relating FPGA system behavior back to RTL
Who should attend?
All engineers/managers involved in military, aerospace, communications, medical or other high reliability designs using FPGAs, you don’t want to miss this informative webinar.
Paul Owens, Senior Corporate Applications Engineer, Synopsys
Paul Owens is a senior CAE within the Synplify Business Group at Synopsys. Paul has worked in Design Automation, CAE, ASIC and FPGA design and verification. He holds a BS in Electrical Engineering from U.C. Berkeley, and an MS in Computer Engineering from Santa Clara University.
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