Accelerate Interface IP Integration for Faster Time-to-Market
With the increasing number of third party IP incorporated into designs and each IP block becoming more complex, it is taking much longer to integrate all of the IP into the SoC. As the complexity of the specifications increases, designers are spending more time learning about the protocols and configuration options than the time spent performing the actual integration. Using customer case studies, this webinar addresses the challenges of integrating PHY and controller IP into an SoC, how the entire IP architecture fits into the SoC using an interface IP subsystem, and the ease of verifying the subsystem through a combined IP verification environment.
Attend this webinar to learn about:
- How expertise in the complex IP configuration options for a particular SoC can improve performance and power
- How using interface IP subsystems has helped designers speed integration and time-to-market
- How protocol expertise helps define the tests and analysis needed for faster design validation
- What designers should expect from their IP subsystem providers
Who should attend:
SoC designers, architects, and managers interested in implementing interface IP
Ralph Grundler joined Synopsys in 2002 and is the product marketing manager for DesignWare IP Prototyping Kits and IP Subsystems. He has worked in interface IP for more than 20 years, designing PCI to PCI bridges, AGP, IRDA, USB and USB OTG IP as well as writing specifications, RTL code and synthesis scripts. Ralph has experience in ASIC, PC and graphics card design as well as worldwide sales and has presented at technical conferences on IP design, IP reuse and IP integration technologies. Ralph holds a Bachelor of Science degree in electronic engineering, majoring in high speed design, from California Polytechnic State University in San Luis Obispo.
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