Even with programmable designs targeting today's fastest FPGAs, achieving aggressive goals for performance, power, and cost can be an overly time consuming task, especially with shrinking product schedules and other development pressures. With the typical design flow involving multiple passes through the implementation process, engineers need a way to shorten subsequent iterations. Verification of larger and larger designs can monopolize engineering resources, especially late in the development process when pressures are greatest. Throughout the design flow, engineers encounter frustrating bottlenecks and technology hurdles.

To provide easier access to the breadth of advances and capabilities that the Virtex®-6 and Spartan®-6 FPGA families offer, the ISE Design Suite 11 provides a complete development flow to support your design methodology and enable you to more quickly complete your FPGA system by streamlining the tasks. As an integral element in the Base Platform of the Xilinx Targeted Design Platform hierarchy, the ISE Design Suite provides unique solutions to help achieve maximum performance for Virtex-6 FPGA applications in less time or to help reduce power and maximize utilization for systems targeting the Spartan-6 FPGA family.

From I/O planning and design entry, through implementation and verification, the ISE Design Suite can help you overcome typical bottlenecks toward achieving your demanding requirements of performance, power, and cost in less time. With industry exclusive technologies such as the PlanAhead Design Analysis Tool, SmartGuide, ChipScope Pro, and the integrated ISE Simulator, users are better able to meet their FPGA design objectives faster.

Web seminar attendees will learn:

  • How to leverage Xilinx exclusive tools, technologies, and IP within the ISE Design Suite to achieve their development goals
  • How to accelerate overall design process, especially for high-speed serial applications, using the ISE Design Suite: Logic Edition

  • Presenter:
    Mark Goosman, Senior Product Marketing Manager
    Mark Goosman is senior product marketing manager for the ISE Design Suite and IP. In this role, Goosman is responsible for outbound marketing of the Xilinx ISE Design Suite, including design tools and IP for logic, DSP, and embedded designers. Goosman joined Xilinx in 1996 and brings over 25 years of experience in the technical software industry where he served in a variety of marketing and sales roles including technical sales, product definition, software development, and technical marketing. Prior to Xilinx, Goosman held various positions at Research Systems, Visual Numerics and Precision Visuals. Goosman holds a bachelor's degree in computer science from Colorado State University.