28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective
This webinar is the last in a series highlighting the 32/28nm design challenges and solutions starting in January 2010. It will be a joint webinar featuring speakers from Synopsys and GLOBALFOUNDRIES.
GLOBALFOUNDRIES will share their perspective on 28nm process technology and design enablement, focusing on their strengths in High K Metal Gate (HKMG) process technology, qualified IP availability and foundry readiness. Synopsys will provide an overview of their 32/28nm design solution and introduce two new in-design technologies benefitting designers at these advanced nodes; In-design STA – final stage leakage recovery, and in-design physical verification – automatic litho-repair using pattern matching technology.
Time permitting; there will be an audience Q&A session with the two speakers after the presentation.
Synopsys Products Featured:
IC Compiler and IC Validator
Who Should Attend:
- Design engineers
- Product line managers
- Place and Route design engineers
- Physical Verification engineers
- Tapeout Engineers
- CAD managers
- Engineering managers
Vice President, IP Ecosystem at GLOBALFOUNDRIES
Walter is responsible for defining, developing and executing strategies, relationships and solutions for GLOBALFOUNDRIES’ third party IP Ecosystem. Previously, at Chartered, Walter led the Design Enablement Alliances team. Prior to joining Chartered, he held senior positions at Sequence Design, Cadence Design Systems and Raytheon. Walter has a B.S. in Electrical Engineering from the University of Massachusetts, Amherst, and an M.B.A from the University of Massachusetts, Boston.
Vice President of Engineering, Synopsys
JC has been with Synopsys for more than 15 years working on various technologies, including RTL Synthesis and Physical Synthesis. Currently, JC leads the placement and clock tree synthesis (CTS) teams for IC Compiler. He holds a Ph.D. degree in Computer Science from State University at New York (SUNY) at Stony Brook.
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