Top 3 Tech Papers – Optimizing DRC and IC Design Flows

We’re sharing three important whitepapers on how to use tools to help you achieve maximum results with an efficient use of resources.

Enable an interface that allows on-demand sign-off design rule checking (DRC) for digital design flows. This empowers physical design and verification engineers to optimize their manual DRC fixes and focus on meeting their power, performance and area (PPA) goals in far less time.

1. Fast, iterative signoff DRC and fixing in P&R


This case study illustrates a solution for fast, iterative, signoff design rule checking (DRC) and fixing during floorplanning and placement. This method not only reduces the total batch DRC iterations, but also eliminates potential late-stage issues during final physical verification signoff that are exponentially harder to fix.

2. Achieve Faster Signoff DRC Convergence in P&R


This paper offers a look at how Qualcomm optimized their IC design flows to achieve maximum efficiency. Using interactive and immediate signoff DRC feedback, they achieve critical milestones such as base layers and metal layers tapeouts inside the P&R environment.

3. Automatic Hotspot Detection and Correction


Manually fixing design for manufacturing (DFM) hotspots outside of the place and route (P&R) process is time-consuming and iterative. In this paper, learn about alternate methods, including GLOBALFOUNDRIES’ automated in-design flow to identify and fix hotspots.


TechOnline 2021