Fill solutions become more challenging at each smaller node because manufacturing processes and physical interactions become more sensitive to small metal density variations. In addition, the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance (due to CMP impact on metal thickness). Meeting all of these constraints requires better analysis to predict the manufacturing and electrical impacts of fill, and more sophisticated algorithms that optimize the use of metal fill features to solve the three fundamental fill issues. This paper defines the requirements and goals of any fill solution, examines the technology behind Mentor’s four fill solutions, and explains how each can be used to satisfy fill requirements, depending on the needs of the design.

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