New embedded FPGA and gate-array style blocks for ASIC System-On-A-Chip devices allow designers to include configurable logic in system. This presents a challenge in several areas. It adds a new axis for architecture and adds complexity to the partitioning of a design. In the area of synthesis and timing closure, the boundary between the ASIC gates and FPGA gates creates a gap in the design flow. New steps are added such as planning for future re-synthesis of FPGA gates in the field. Additional work must be carried out in implementing Design-For-Test and integrating FPGA test coverage into the ASIC. This article provides a heads-up for engineers who have not explored this kind of system, and will also present some proposed methodologies for handling these issues based on the design of a technology demonstrator device.