Five key workflows that deliver 3D IC packaging success
Several factors are converging and driving the chiplet design revolution. This paper explores these factors and outlines five key workflows that address and manage the associated, new challenges. The paper recommends workflow adoption focus areas that provide immediate heterogeneous integration capability benefits while establishing a managed methodology adoption and migration process that minimizes disruption, risk, and cost. This will bring heterogeneous integration-based chiplet design within reach of the mainstream instead of being accessible only to mega iDMs (integrated device manufacturers) and fabless semiconductor companies.
- Adapting to design with chiplets
- Early planning and predictive analysis
- Hierarchical chiplet co-optimization
- Chiplet interface management and design
- Automating interface-based design
- Thermal, stress, and reliability management
- Test and testability
- Driving verification and signoff
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