VLSI Implementation of CS-ACELP Vocoder Algorithm
This paper takes a look at the implementation of vocoder in a chip. The objective of the project is to design the architecture for implementation of CS-ACELP encoder and decoder recommended by G.729 ITU-T standard. The architecture proposed is using VHDL. As the chip is exclusively designed for the compression, the high speed and power requirements constraints are met by parallel processing of the DSP algorithm with less dedicated hardware. A MATLAB implementation of G.729 algorithm was done and the inputs and the intermediate vectors from the MATLAB implementation were used as reference for verification.
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