Xilinx® Virtex-4™ devices have a 64-tap absolute delay element built in each I/O, making high-speed memory interface read data capture very easy. This feature also provides the flexibility to adopt different read data capture schemes where clock/strobe or data can be delayed. This article explains how Virtex-4 devices make challenging memory interface requirements simple.

Reprinted with permission from Xcell Journal / Spring 2005. Article © Xcell Journal.