Although ASIC design methodology has been used for more than thirty years, today’s designers working with very deep ASIC submicron technology face a new set of technical challenges. These include leakage power, timing closure, signal integrity and design for testability. To efficiently address these issues, leading EDA vendors incorporate advanced design and verification techniques that help ASIC designers to improve the chance of first-time-right design success. This paper describes the very deep submicron ASIC design methodology that is designed to produce 100% first-pass silicon and on-schedule delivery results.