Verifying Your Logic Design for First-Time Success
When Xilinx invented the FPGA in the mid 1980s, the preferred way to verify a design was to program the FPGA in the actual system and see if it operated properly from both a timing and functional standpoint.
Those days are long gone.
According to a 2005 EDA study by CMP Media, verification is one of the top three considerations for FPGA designers. A fast and successful verification experience is essential to get your product to market on time. But how do you know if your current flow is the best choice, especially for today’s high-density FPGAs? At a minimum, a sound verification strategy should include static/dynamic timing and dynamic simulation. Optional advanced methodologies such as equivalency checking and assertion-based verification are now also available to Xilinx FPGA users.
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