Verifying Security Aspects of SoC Design with Jasper
This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Complex system-on-chips contain secure information that is vulnerable to unauthorized access. Verifying whether the secure information can be leaked is hard to achieve with conventional RTL validation methods. The security requirements are not easily expressible by regular SVA assertions; therefore, it is not practical to achieve validation with standard formal verificationtools. Jasper’s Security Path Verification App (SPV) is part of a wide spectrum of apps provided for design and verification domains.
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