Electric and Electronic systems account for 49.2% of registered breakdowns (source: Allgemeiner Deutscher Automobil Club, 2003). Recent statistics on ICs said that 71% of System-on-Chip (SoC) re-spins are due to functional bugs, and 47% of them are due to incorrect or incomplete specifications. Moreover, 14% of failing SoCs have bugs in reused components or IPs. This is why 60-70% of the entire product cycle for a complex chip is dedicated to verification tasks.

But real systems are in fact mixed-signal and here functional verification always requires the interaction between the different methodologies needed to verify the digital elements and the analog ones.

Yogitech’s proposed approach combines digital and analog verification, providing verification engineers with a methodology and a set of intellectual properties to interface Specman Elite with a mixed-signal (multi-language) simulator building a mixed-signal verification environment able to manage high level models and spice level net-list.