When verification is not under control, project schedules slip, quality is jeopardized and the risk of re-spins soars. These less-than-stellar outcomes seem to be happening more and more often. First-time success with silicon is waning, down from nearly 40% in 2002 to less than 30% in 2007, according to an independent verification survey funded by Mentor Graphics. Re-spins are mainly due to functional or logical flaws in the design, which suggests an increasing number of problems in the overall verification management process. There are three dimensions to any IC design project: the process, the tools and the data. Any comprehensive approach to verification management needs to handle them all.
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