Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps, 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm process. While this architecture is undoubtedly faster, larger, and lower power per bit, just how does one go about interfacing a DDR3 SDRAM DIMM to a field programmable gate array (FPGA)? Leveling is the key word. Without having the leveling feature built directly into the FPGA I/O structure, interfacing anything to a DDR3 SDRAM DIMM is going to be complicated, costly, and involve numerous external components.
This paper describes leveling, including read leveling and write leveling, and why it is important. It also discusses other FPGA innovations, including Dynamic OCT, Variable Delay for DQ Deskew, and Reliable Capture, and shows how high-performance FPGAs complement high-performance DDR3 SDRAM DIMMs by providing high-memory bandwidth, improved timing margin, and great flexibility in system design.
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