Using Tessent Low Power Test to Manage Switching Activity
Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, increasing integration between analog and digital blocks, and diminishing supply voltages. Both this complexity and the need for energy efficiency in portable and wireless IC designs are increasing the level of concern over power use and power control during test. Attempts to manage power are being made at both the design and functional levels. Using the techniques outlined in the paper, scan shift switching can typically be reduced from 50% to 25% with minimal impact on test time. Capture switching activity can also be reduced by a significant amount, but the switching activity reduction as well as the impact on test time is highly design dependent.
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