Using System Generator for Systematic HDL Design, Verification, and Validation
Xilinx System Generator is a MATLAB Simulink blockset that facilitates the design and targeting of Xilinx FPGAs. Within the MATLAB environment familiar to DSP designers, System Generator provides the ability to functionally simulate a design and use the MATLAB environment to verify the bit/cycle-true model against the golden reference results produced either externally or inside the MATLAB environment.
Within MATLAB, designers can both target a Xilinx FPGA hardware platform and verify the hardware output, making it easier for an algorithm developer to make the leap into hardware and a firmware developer to better grasp the algorithm. However, despite the appreciable design cycle reduction advantages, some design philosophies built around pure HDL are slow to
benefit—primarily due to legacy HDL design
methodologies, designers’ reluctance to stray from their
comfort zone, and a lack of familiarity with Simulink.
The benefit being overlooked is that System Generator
complements the HDL design task by providing an easy-to-configure test bench platform for both functional
simulation and hardware verification.
This paper provides an overview of System Generator, an example test bench, and a systematic approach to using System Generator in HDL design.
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