As FPGA capacities exceed millions of gates, a problem surfaces that looks very familiar to ASIC designers. The physical effects of routing and interconnect become the dominant factors in the final performance of the chip, while device delays become largely irrelevant. A word of warning, however, to engineers proficient in the techniques used to negate the problems faced in the ASIC space. Be aware that while the problems may look similar, the solutions and tools used to solve the same issues in the FPGA space are quite different. While the key consideration is still: “it’s not what the device is, but where it is”, there are other factors of importance, as this paper will explain. Trying to achieve FPGA timing closure in the traditional way, without the correct application of physical synthesis techniques, not only results in less than optimal performance but will also end up as a painful and unpredictably long process involving many place-and-route iterations. This paper outlines some real-world case studies explaining how to correctly apply physical synthesis using, as examples, the technologies driving Mentor Graphics’ Precision family of products.

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