Today’s FPGA designs are becoming larger and more complex, with hundreds of macros, Intellectual Properties, and reusable parts of legacy designs. FPGA designers now face the huge challenge of rapidly describing the interfaces, i.e. hierarchies and interconnections, for a new design using these parts. However, traditional approaches spend too much time drawing large block diagrams or writing thousands of lines of structural HDL.

This paper describes how the spreadsheet approach of Interface-Based Design in FPGA Advantage can enable design engineers to construct their FPGA design from the various sources for blocks (unique HDL code, IP cores, legacy HDL code, FPGA Vendor cores, etc.) rapidly and efficiently, while also preparing for design documentation.

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