Using HLLs to Develop DSP Applications
This paper describes issues and techniques used in the development of DSP algorithms using high-level languages (HLLs). DSP algorithms have traditionally been implemented by hand crafted assembler in order to gain optimal performance out of the architectures. The work has been carried out by a relatively specialized set of engineers that combine the unusual skills of a good mathematical understanding of the algorithm as well as being able to code at a low level in assembly language. Apart from the problems of finding and keeping such engineers, the code is much less maintainable and slower to write than code developed in a high level language. For these reasons it is highly desirable to find ways of implementing DSP algorithms in high level languages. This becomes increasingly true as the overall complexity and size of DSP algorithms continues to increase.
Another very strong driver for good compiler technology for DSP architectures is that many of the highly complex algorithms being standardized by bodies such as ISO, ETSI and the ITU are written in C and a C model effectively forms the specification. In order to implement these algorithms this ‘model’ code is an excellent way to get an implementation working very quickly on an architecture. Ultimately, it would be desirable to take the code from the standards body, run it through the compiler, and have a real-time working implementation just as efficient as that provided by the hand crafted assembler. In reality, if we could get to within say 20% of the handcrafted code using this approach, then this would probably be sufficient to no longer justify hand coding. In many cases the extra 20% (or close to it) could be gained by simply profiling the code and optimizing certain parts.
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