Using High-Level Synthesis for FPGA Development
Designing the hardware to support next generation communication systems (such as Super 3G and WiMAX) has become increasingly complicated. To implement these demands into an ASIC or FPGA, one must consider tradeoffs between design time, the size of the silicon implementation, and performance of the final system. Even more challenging, one must complete these larger, more complex designs quickly to meet their narrow time-to-market windows.
This paper introduces a solution: a new design methodology using C-Based design. The paper describes Fujitsu’s evaluation of Mentor Graphics’ Catapult C Synthesis tools for field programmable gate array (FPGA) development and compares its results to a conventional RTL design flow. The result is a substantial reduction of design time with the use of Catapult C Synthesis.
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