Using FormalPro for Xilinx Verification in a Precision RTL Flow
This document describes how to verify Xilinx FPGA designs using FormalPro. Specifically, the flow available in FormalPro is for Xilinx Virtex family designs implemented with Precision RTL and Xilinx ISE. You can use FormalPro to verify other families of Xilinx devices; however, this verification flow has been used primarily for designs targeted to Xilinx Virtex II.
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