This document describes how to verify Actel FPGA designs using FormalPro. Specifically, the flow available in FormalPro is for Actel A54SX, A54SAX, Axcelerator and ProASIC family designs implemented with Precision RTL and Actel Designer. You can use FormalPro to verify other families of Actel devices; however, this verification flow has been used primarily for designs targeted to the above.

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