Using CRC Hard Blocks in Virtex-5 FPGAs
Data corruption is the principal problem associated with data transmission and storage. It is essential that a receiving module be able to differentiate between an error-free message and an erroneous one. There are various methods for detecting errors; most error-checking methods do so by introducing redundant bits exclusively for this purpose. Commonly used methods for error detection in data communication include parity codes, Hamming codes, and cyclic redundancy check (CRC); of these, CRC is the most widely used.
CRC is computed on a given set of data bits and appended at the end of the data frame before transmission or storage. When the frame is received or retrieved, its validity is verified by recalculating the CRC for the contents of the frame to ensure that the data is error-free. This article takes a quick look at the theory behind CRC calculation and its hardware implementation using linear feedback shift registers. It also discusses the CRC hard block present in Xilinx Virtex-5 LXT/SXT devices.
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